1. Field of the Invention
The present invention relates to an integrated photoelectric receiving device in which a PIN-type photodetector and a junction field effect transistor (FET) for a pre-amplifier stage are integrated in a single chip, and a method of manufacturing the same.
2. Description of the Prior Art
In general, importants in determining the structure of such a integrated photoelectric receiving device or element are two kinds of processes achieved with differential structure and processing techniques, that is, independently optimizing the structure and process of a photodetector and a transistor, and electrically connecting the photodetector and the transistor.
Referring to FIG. 1, there are sequentially illustrated various examples of the integrated structure of such an integrated photoelectric receiving device presently disclosed.
More specifically, the structures of such a photoelectric receiving device are defined as below. That is, (a) a common epitaxial layer structure in which the photodetector and the transistor use commonly the same epitaxial layer (FIG. 1(a)); (b) an uneven structure integrated without respect to the difference in height of the photodetector and the transistor (FIG. 1(b)); (c) a recess trench structure in which a photodetector forming area is etched and the photodetector and the transistor are same in height (FIG. 1(c)); (d) a structure in which an edge of the device is tapered to reduce a step on the etched portion (FIG. 1(d)); (e) a buried planar buried structure in which the photodetector is buried to provide a complete planar shape (see FIG. 1(e)); (f) a compatible planar structure in which a planar photodetector is employed to assure a compatibility with planar electronic components in structure and process (FIG. 1(f)); and, (g) a structure in which the above-mentioned uneven and trench structures are composited (see FIG. 1(g)).
The common epitaxial layer structure of FIG. 1(a) is defined such that a single InGaAs layer is grown on a semi-dielectric InP substrate and a PIN-type photodetector element and a junction FET are then integrated over the entire surface of the substrate. This is referred to an initial structure including the first photoelectric receiving element.
According to the structure in FIG. 1(a), there is an advantage that a single epitaxial growing process is executed to obtain the same structure. But, differencies are presented in a doped density of a channel impurity and a thickness between the PIN-type photodetector and the transistor. As a result, it is difficult to assure an independent optimization in structure of the element and, therefore, the performance of the element is deteriorated undesirably.
In the uneven structure shown in FIG. 1(b), a n-channel layer of the PIN-type photodetector is used as an electrode contact layer or channel layer of the FET so as to manufacture the device through a single epitaxial growing process. Further, because the channel layer of the transistor is different from an absorption layer of the photodetector, it is possible to independently optimize the transistor and photodetector.
With the preveously noted uneven structure, if the PIN-type photodetector is respectively thick, it is difficult to execute a fine lithography or wiring process. Further, an important in this case is that different condition must be employed to selectively etch the n-channel layer and absorption layer of the photodetector. Similar to the common epitaxial layer structure, this uneven structure has a problem resulted from a parastic capacitance presented on the wiring.
Accordingly to the trench structure shown in FIG. 1(c), because the photodetector is thicker than the transistor by 2 to 3 .mu.m, a trench having a depth of 2 to 3 .mu.m is formed on the semi-dielectric substrate to provide the same height of the photodetector and transistor and then the photodetector is buried in the trench.
With this trench structure, there is an advantage that a fine lithographic process can be easily executed. But, it is difficult to assure the electrical connection between the photodetector and the transistor, and a wiring capacitance is relatively reduced.
Meanwhile, in the tapered structure to reduce the surface step, as shown in FIG. 1(d), the problems resulted from the fine lithographic and wiring process as well as the wiring parastic capacitance can be solved effectively.
Accordingly, the device having this structure has an excellent performance. But, it is troubled to fabricate such a structure using an ion beam etching process.
According to the buried planar structure shown in FIG. 1(e), the fine lithographic process and a wiring process can be easily achieved and the parastic capacitance on the wire can be also reduced effectively without the problem related to the surface step. The integrated photoelectric device having such a tapered structure is fabricated by way of a method of filling the etched trench by using a property of a liquid epitaxy growing process, a method of using two ion beam etching processes, or a method of using a selective organic metal varpor epitaxy growing process (OMVEG). But, according to the liquid epitaxy growing process, an area of the photodetector is limited undesirably. In case of the ion beam etching process, it requires a very restricted control of the process. Further, according to the selective epitaxy method, a polycrystal structure can be grown over a material employed as a mask and an overgrow may be occurred on edge of the region to be grown.
In the compatible planar structure shown an FIG. 1(f), a planar photodetector which employs the substrate itself as an absorption layer is integrated with a transistor such as a MESFET. As a result, it can achieves the simple manufacturing process and the planar structure can be preferably obtained.
But, because the development for such a planar photodetector is presently incomplete, it is difficult to be employed to an InP-base device using InGaAs epitaxial layer as an absorption layer.
As shown in FIG. 1(g), the composite structure having properties of the uneven and the trench structures is achieved by integrating an uneven PIN-type photodetector and a junction FET. With this sturcture, it has an advantage that the property of the photodetetor and transistor can be simultaneously maximized by using two epitaxial crystal growing processes and a selective wet etching process.
With this composite structure, however, a distance between a gate and a source of the transistor is restrictedly defined. By the reason, it is difficult to maximize the performance of the device. Further, two lithographic processes are executed to form the gate. As a result, a reproduction or yield of the device is deteriorated undesirably.
In addition to the above-mentioned structures, there has been disclosed a vertical structure in which a PIN-type photodetector is formed on a n-type photodetector is formed on a n-type substrate, a semi-dielectric layer is epitaxially grown over the entire surface of the substrate and ion injection is then executed to the entire structure to obtain a FET element. Also, there have been disclosed a structure in which an InGaAs photodetector and a GaAs MESFET are integrated on a GaAs substrate by way of a lattice non-alining epitaxial process and a structure in which a GaAs MESFET is formed on an InP substrate.
For example, U.S. Pat. No. 4,830,986, issued to Richard. G. S. Plumb, etc., discloses a ridge waveguide laser structure is manufactured by a method including providing a photoresist stripe on an exposed area of a cap layer of a multilayer laser wafer; etching channels through the cap layer and a p passive layer using the stripe and an oxide layer window as a mask; evaporating a passivating and insulating oxide over the wafer, there being breaks in the oxide where the stripe is undercut during channel etching; and removing the stripe and the oxide on it by a lift-off technique.
Moreover, U.S. Pat. No. 4,888,784 assigned to shoji Hirata discloses a semiconductor laser device including a first semiconductor layer having a strip waveguide structure to obtain optical confinement and a second semiconductor layer having a ridge waveguide structure for defining an electrical current passage region. The strip waveguide structure has a first width, and projects on the first semiconductor layer, extending over the central area of the layer in a longitudinal direction. The ridge waveguide structure projects on the second semiconductor layer and extends in the longitudinal direction with a second width which corresponds to the strip structure. The strip waveguide structure cooperates with the ridge waveguide structure to produce a difference between the refractive index of a center region which extends in the longitudinal direction of the second semiconductor and that of a neighboring region due to the difference in thicknesses between the two, so that the center region serves as an optical waveguide.